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1 ? fn6221.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners. isl29004 light-to-digital output sensor with address selection, hi gh sensitivity, gain selection, interrupt function and i 2 c interface the isl29004 is an integrated lig ht sensor with a 16-bit integrating type adc, i 2 c user programmable lux range select for optimized counts/lux, and i 2 c multi-function control and monitoring capabilities. the internal adc provides 16-bit resolution while rejecting 50hz and 60hz flicker caused by artificial light sources. in normal operation, power consumption is typically 300a. futhermore, an available software power-down mode controlled via the i 2 c interface reduces power consumption to less than 1a. the device also support a hardware interrupt that remains asserted low until the host clears it through i 2 c interface. the isl29004 is in an 8 ld odfn package and has two i 2 c address pins for multiple devices on the same bus. the isl29003 is a similar light sensor with a hardwired i 2 c address that is available in odfn6 package. designed to operate on supplies from 2.5v to 3.3v, the isl29004 are specified for op eration over the -40c to +85c ambient temperature range. pinout isl29004 (8 ld odfn) top view features ? range select via i 2 c - range1 = 1000lux - range2 = 4000lux - range3 = 16,000lux - range4 = 64,000lux ? human eye response (540nm peak sensitivity) ? temperature compensated ? 16-bit resolution ? adjustable resolution: up to 65 counts per lux ? user-programmable upper and lower threshold interrupt ? simple output code, dire ctly proportional to lux ? 50hz/60hz rejection ? 2.5v to 3.3v supply ? 8 ld odfn (3mmx3mm) ?i 2 c address selection applications ? ambient light sensing ? backlight control ? temperature control systems ? contrast control ? camera light meters ? lighting controls block diagram ordering information part number (note) tape & reel package (pb-free) pkg. dwg. # isl29004iroz - 8 ld odfn mdp0052 ISL29004IROZ-T7 7? 8 ld odfn tape and reel mdp0052 isl29004iroz-evalz evaluation board (pb-free) note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. sda scl int vdd gnd rext 1 2 3 4 8 7 6 5 thermal pad a0 a1 rext gnd scl sda command register integrating adc data register i 2 c photodiode 1 photodiode 2 mux 3 2 8 7 1 fosc iref counter 2 16 mode gain/range ext shdn int time 6 int interrupt isl29004 timing int a1 a0 4 5 data sheet december 21, 2006
2 fn6221.0 december 21, 2006 absolute maxi mum ratings (t a = +25c) v dd supply voltage between v dd and gnd . . . . . . . . . . . . . 3.6v i 2 c address pin voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to 3.6 i 2 c bus pin voltage (scl, sda) . . . . . . . . . . . . . . . . . -0.2v to 5.5v i 2 c bus pin current (scl, sda) . . . . . . . . . . . . . . . . . . . . . . <10ma r ext pin voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to 3.6v maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-45c to +100c operating temperature . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c esd, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv esd, machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500v caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v dd = 3v, t a = +25c, r ext = 100k 1% tolerance, unless otherwise s pecified, internal timing mode operation (see principles of operation). parameter description condition min typ max unit v dd power supply range 2.25 3.63 v i dd supply current 0.29 0.33 ma i dd1 supply current disabled software disabled 0.1 1 a f osc1 internal oscillator frequency gain/range = 1 or 2 290 327 364 khz f osc2 internal oscillator frequency gain/range = 3 or 4 580 655 728 khz fi 2 ci 2 c clock rate (note 2) 1 400 khz data0 diode1 and diode2 dark adc code e = 0lux, mode1, gain/range = 1 1 5 counts data1 full scale adc code 65535 counts data2 diode1 adc code gain/range = 1 accuracy mode0 e = 300lux, fluorescent light, gain/range = 1 (note 1) 13,800 20,200 24,400 counts data3 diode2 adc code gain/range = 1 accuracy mode1 2,020 counts data4 diode1 adc code gain/range = 2 accuracy mode0 e = 300lux, fluorescent light, gain/range = 2 (note 1) 5,050 counts data5 diode2 adc code gain/range = 2 accuracy mode1 505 counts data6 diode1 adc code gain/range = 3 accuracy mode0 e = 300lux, fluorescent light, gain/range = 3 (note 1) 1,262 counts data7 diode2 adc code gain/range = 3 accuracy mode1 126 counts data8 diode1 adc code gain/range = 4 accuracy mode0 e = 300lux, fluorescent light, gain/range = 4 (note 1) 316 counts data9 diode2 adc code gain/range = 4 accuracy mode1 32 counts v ref voltage of r ext pin 500 mv v tl scl, sda, a0 and a1 threshold lo (note 3) 1.05 v v th scl and sda threshold hi (note 3) 1.95 v i sda sda current sinking capability 3 5 ma i int int current sinking capability 3 5 ma i il a0 and a1 input current lo a0 = a1 = gnd 0.1 a i ih a0 and a1 input current hi a0 = a1 = v dd 0.1 a notes: 1. fluorescent light is substitut ed by a white led during production. 2. minimum i 2 c clock rate is guaranteed by design. 3. the voltage threshold levels of the sda and scl pins are vdd dependent: v tl = 0.35*v dd . v th = 0.65*v dd . isl29004
3 fn6221.0 december 21, 2006 pin descriptions pin number isl29003 pin number isl29004 pin name description 1 1 vdd positive supply; connect this pin to a regulated 2.5v to 3.3v supply 2 2 gnd ground pin. 3 3 rext external resistor pin for adc referenc e; connect this pin to ground through a (nominal) 100k resistor 46 int interrupt pin; lo for interrupt/alarming. the int pin is an open drain. 57scli 2 c serial clock the i 2 c bus lines can pulled above vdd, 5.5v max. 68sdai 2 c serial data n/a 4 a0 bit 0 of the i 2 c address. the address pins have an open gate equivalent circuit. these are the least-significant bits of the i 2 c address. the 4 possible addresses are 44(hex) through 47(hex). n/a 5 a1 bit 1 of the i 2 c address. isl29004
4 fn6221.0 december 21, 2006 principles of operation photodiodes the isl29004 contain two photodiodes. diode1 is sensitive to both visible and intrared light, while diode2 is mostly sensitive to infrared light. the spectral response of the two diodes are independent from one another. see figure spectral response vs wavelength in the performance curves section. the photodiodes convert light to current. then, the diodes? current outputs are conver ted to digital by a single built-in integrating type 16-bit analog-to-digital converter (adc). an i 2 c command mode determines which photodiode will be converted to a digital signal. mode0 is diode1 only. mode1 is diode2 only. mode3 is a sequential mode0 and mode1 with an internal subtra ct function (diode1 - diode2). analog-to-digital converter. the converter is a charge-balancing integrating type 16-bit adc. the chosen method for conversion is best for converting small current signals in the presense of an ac periodic noise. a 100ms integration time, for instance, highly rejects 50hz and 60hz power line noise simultaneously. see integration time and noise rejection section. the built-in adc offers user flexibility in integration time or conversion time. two timing modes are available. internal timing mode and external timing mode. in internal timing mode, integration time is determ ined by an internal dual speed oscillator (fosc), and the n-bit (n = 4, 8, 12,16) counter inside the adc. in external timing mode, integration time is determined by the time between two consecutive i 2 c external timing mode commands. see external timing mode example. a good balancing act of integration time and resolution depending on the application is required for optimal results. the adc has four i 2 c programmable range select to dynamically accomodate various lighting conditions. for very dim conditions, the adc can be configured at its lowest range. for very bright condit ions, the adc can be configured at its highest range. interrupt function the active low interrupt pin is an open drain pull-down configuration. the interrput pin serves as an alarm or monitoring function to determine whether the ambient light exceeds the upper threshold or goes below the lower threshold. the user can also configure the persistency of the interrupt pin. this eliminates any false triggers such as noise or sudden spikes in ambient light conditions. an unexpected camera flash for example can be ignored by setting the persistency to 8 integration cycles. i 2 c interface there are eight (8) 8-bit registers available inside the isl29004. the command and control registers define the operation of the device. the command and control registers do not change until the r egisters are overwrit ten.there are two 8- bit registers that set the high and low interrupt thresholds. there are four 8-bit data read only registers. two bytes for the sensor reading and another two bytes for the timer counts. the data registers contain the adc's latest digital output, and the number of clock cycles in the previous integr ation period. the isl29004?s i 2 c interface slave address is pin-selectable by pins a0 and a1. these pins can be tied or driven either high or low. they comprise the least-significant two bits of the i 2 c address, while the 5 most-significant bits are hardwired as 100001{a1}{a0}. the four possible addresses are therefore 44(hex ) through 47(hex). the isl29003?s i 2 c interface slave address is hardwired internally as 44(hex). figure 1 shows a sample one-byte read. figure 2 shows a sample one-byte write. figure 3 shows a sync_iic timing diagram sample for externally controlled integration time. the i 2 c bus master always drives the scl (clock) line, while either the master or the slave can drive the sda (data) line. every i 2 c transaction begins with the master asserting a start condition (sda falling while scl remains high). the following byte is driven by the master, and includes the slave address and read/write bit. the receiving device is responsible for pulling sda low during the acknowledgement period. every i 2 c transaction ends with th e master asserting a stop condition (sda rising while scl remains high). for more information about the i 2 c standard, please consult the philips ? i 2 c specification documents. isl29004
5 fn6221.0 december 21, 2006 figure 1. i 2 c read timing diagram sample start w aa aa a6 a5 a4 a3 a2 a1 a0 w a r7 r6 r5 r4 r3 r2 r1 r0 a a6 a5 a4 a3 a2 a1 a0 w a a a a d7d6d5d4d3d2d1d0 a 123456789123456789 123456789123456789 i 2 c sda in sda driven by master register address i 2 c sda out device address i 2 c data sda driven by master i 2 c clk stop stop start sda driven by master device address sda driven by isl29003 data byte0 nak figure 2. i 2 c write timing diagram sample start w aaa a6 a5 a4 a3 a2 a1 a0 w a r7 r6 r5 r4 r3 r2 r1 r0 a b7 b6 b5 b4 b3 b2 b1 b0 a aaa 123456789123456789123456789 stop sda driven by master functions register address device address i 2 c data sda driven by master sda driven by master i 2 c sda in i 2 c clk in i 2 c sda out figure 3. i 2 c sync_iic timing diagram sample start w aastop a6 a5 a4 a3 a2 a1 a0 w a r7 r6 r5 r4 r3 r2 r1 r0 a aa 123456789123456789 i 2 c sda in i 2 c clk in sda driven by master i 2 c sda out device address i 2 c data register address sda driven by master isl29004
6 fn6221.0 december 21, 2006 register set there are eight registers that are available in the isl29004. table 1 summarizes the available registers and their functions. table 1. register set addr (hex) register name bit(s) function name functions/description 00 command 7 enable 0: disable adc-core 1: enable adc-core 6 adcpd 0: normal operation 1: power down mode 5 timing_mode 0: integration is internally timed 1: integration is externally sync/controlled by i 2 c host 4 reserved 3:2 mode<1:0> selects adc work mode 0: diode1?s current to unsigned 16-bit data 1: diode2?s current to unsigned 16-bit data 2: difference between diodes (i1 - i2) to signed 15-bit data 3: reserved 1:0 width<1:0> number of clock cycles; n-bit resolution 0: 2 16 cycles 1: 2 12 cycles 2: 2 8 cycles 3: 2 4 cycles 01 control 7 ext_mode always set to logic 0. factory use only. 6 test_mode always set to logic 0 5 int_flag 0: interrupt is cleared or not yet triggered 1: interrupt is triggered 4 reserved always set to l ogic 0. factory use only. 3:2 gain<1:0> selects the gain so range is 0: 0 - 1000lux 1: 0 - 4000lux 2: 0 - 16000lux 3: 0 - 64000lux 1:0 int_persist <1:0> interrupt is triggered after 0: 1 integration cycle 1: 4 integration cycles 2: 8 integration cycles 3: 16 integration cycles 02 interrupt threshold hi 7:0 interrupt threshold hi high byte of hi interrupt threshold. default is 0xff 03 interrupt threshold lo 7:0 interrupt threshold lo high byte of the lo interrupt threshold. default is 0x00 04 lsb_sensor 7:0 lsb_sensor read-only data register t hat contains the least si gnificant byte of the latest sensor reading 05 msb_sensor 7:0 msb_sensor read-only data register t hat contains the most si gnificant byte of the latest sensor reading 06 lsb_timer 7:0 lsb_timer read-only data register that contains the least si gnificant byte of the timer counter value corresponding to the latest sensor reading. 07 msb_timer 7:0 msb_timer read-only data register that contains the most si gnificant byte of the timer counter value corresponding to the latest sensor reading. isl29004
7 fn6221.0 december 21, 2006 d command register 00(hex) the read/write command register has five functions: (1) enable; bit 7.this function either resets the adc or enables the adc in normal operation. a logic 0 disables adc to reset-mode. a logic 1 enables adc to normal operation. (2) adcpd; bit 6. this function puts the device in a power down mode. a logic 0 puts the device in normal operation. a logic 1 powers down the device. (3) timing mode; bit 5. this function determines whether the integration time is done internally or externally. in internal timing mode, integration time is determined by an internal dual speed oscillator (fosc), and the n-bit (n = 4, 8, 12,16) counter inside the adc. in external timing mode, integration time is determined by the time between two consecutive external-sync sync_iic pules commands. (4) photodiode select mode; bits 3 and 2. this function controls the mux attached to the two photodiodes. at mode0, the mux directs the current of diode1 to the adc. at mode1, the mux directs the current of diode2 only to the adc. mode3 is a sequential mode0 and mode1 with an internal subtract function (diode1 - diode2). * n = 4, 8, 12,16 depending on the number of clock cycles function. (5) width; bits 1 and 0. this function determines the number of clock cycles per conversion . changing the number of clock cycles does more than just change the resolution of the device. it also changes the integration time, which is the period the device?s analog-to-digital (a/d) converter samples the photodiode current signal for a lux measurement. control register 01(hex) the read/write control register has three functions: (1) interrupt flag; bit 5. this is the status bit of the interrupt. the bit is set to logic high when the interrupt thresholds have been triggered, and logic low when not yet triggered. writing a logic low clears/resets the status bit. (2) range/gain; bits 3 and 2. the full scale range can be adjusted by an external resistor rext and/or it can be adjusted via i2c using the gain/range funtion. gain/range has four possible values, range(k) where k is 1 through 4. table 9 lists the possible values of range(k) and the resulting fsr for some typical value r ext resistors. when gain/range is set to range1 or range2, the fosc runs at 327khz. when gain/range is set to range3 or range4 fosc runs at twice the rate at 655khz. the automatic fosc adjustment feature improves si gnal-to-noise ratio for low lux measurements. table 2. write only registers address register name functions/ description b1xxx_xxxx sync_iic writing a logi c 1 to this address bit ends the current adc-integration and starts another. used only with external timing mode. bx1xx_xxxx clar_int writing a logic 1 to this address bit clears the interrupt. table 3. enable bit 7 operation 0 disable adc-core to reset-mode (default) 1 enable adc-core to normal operation table 4. adcpd bit 6 operation 0 normal operation (default) 1 power down table 5. timing mode bit 5 operation 0 internal timing mode. integration time is internally timed determined by fosc, rext, and number of clock cycles. 1 external timing mode. integration time is externally timed by the i2c host. table 6. photodiode select mode; bits 2 and 3 bits 3:2 mode 0:0 mode0. adc integrates or converts diode1 only. current is converted to an n-bit unsigned data.* 0:1 mode1. adc integrates or coverts diode2 only. current is converted to an n-bit unsigned data.* 1:0 mode3. a sequential mode0 then mode1 operation. the difference current is an (n-1) signed data.* 1:1 no operation. table 7. width bits 1:0 number of clock cycles 0:0 2^16 = 65,536 0:1 2^12 = 4,096 1:0 2^8 = 256 1:1 2^4 = 16 table 8. interrupt flag bit 5 operation 0 interrupt is cleared or not triggered yet 1 interrupt is triggered isl29004
8 fn6221.0 december 21, 2006 interrupt persist; bits 1 and 0. the interrupt pin and the interrupt flag is triggered/set w hen the data sensor reading is out of the interrupt threshold window after m consecutive number of integration cycles. the interrupt persist bits determine m. interrupt threshold hi register 02(hex) this register sets the the hi threshold for the interrupt pin and the interrupt flag. by defaul t the interrupt threshold hi is ff(hex). the 8-bit data written to the register represents the upper msb of a 16-bit value. the lsb is always 00(hex). interrupt threshold lo register 03(hex) this register sets the the lo threshold for the interrupt pin and the interrupt flag. by default the interrupt threshold lo is 00(hex). the 8-bit data written to the register represents the upper msb of a 16-bit value. the lsb is always 00(hex). sensor data register 04(hex) and 05(hex) when the device is configured to output a 16-bit data, the most significant byte is access ed at 04(hex), and the least significant byte can be access ed at 05(hex). the sensor data register is refreshed after very integration cycle. timer data register 06(hex) and 07(hex) note that the timer counter value is only available when using the external timing m ode. the 06(hex) and 07(hex) are the lsb and msb respectively of a 16-bit timer counter value corresponding to the most recent sensor reading. each clock cycle increments the counter. at the end of each integration period, the value of this counter is made available over the i 2 c. this value can be used to eliminate noise introduced by slight timing errors caused by imprecise external timing. microcontrolle rs, for example, often cannot provide high-accuracy command-to-command timing, and the timer counter value can be used to eliminate the resulting noise. calculating lux the isl29004?s output codes, data, are directly proportional to lux. the proportionality constant is determined by the full scale range, fsr, and the n-bit adc which is user defined in the command register. the proportionality constant can also be viewed as the resolution; the smallest lux measurement the device can measure is . full scale range, fsr, is determined by the software programmable range/gain, range(k), in the command register and an external scaling resistor r ext which is referenced to 100k . the transfer function effectively for each timing mode becomes: internal timing mode external timing mode n = 4, 8, 12, or 16. this is the number of clock cycles programmed in the command register. range(k) is the user defined range in the gain/range bit in the command register. r ext is an external scaling resistor hardwired to the r ext pin. data is the output sensor r eading in number of counts available at the data register. 2 n represents the maximum number of counts possible in internal timing mode. for the external timing mode the table 9. range/gain typical fsr lux ranges bits 3:2 k range(k) fsr lux range@ r ext = 100k fsr lux range@ r ext = 50k fsr lux range@ r ext = 500k 0:0 1 973 973 1946 195 0:1 2 3892 3892 7784 778 1:0 3 15,568 15,568 31,136 3114 1:1 4 62,272 62,272 124,544 12,454 table 10. interrupt persist bits 1:0 number of integration cycles 0:0 1 0:1 4 1:0 8 1:1 16 table 11. data registers address (hex) contents 04 least-significant byte of mo st recent sensor reading. 05 most-significant byte of most recent sensor reading. 06 least-significant byte of timer counter value corresponding to most recent sensor reading. 07 most-significant byte of timer counter value corresponding to most recent sensor reading. e data = (eq. 1) fsr 2 n ------------ = (eq. 2) (eq. 3) fsr range k () 100k r ext ------------------ = (eq. 4) e range k () 100k r ext ------------------ 2 n ---------------------------------------------------- data = (eq. 5) e range k () 100k r ext ------------------ counter ---------------------------------------------------- data = isl29004
9 fn6221.0 december 21, 2006 maximum number of counts is stored in the data register named counter counter is the number increments accrued for between integration time for external timing mode. gain/range, range(k) the gain/range can be programmed in the control register to give range (k) determining the fsr. note that range(k) is not the fsr. see equation 3. range(k) provides four constants depending on programmed k that will be scaled by r ext . see table 9. unlike r ext , range(k) dynamically adjusts the fsr. this function is especially useful when light conditions are varying drastically while maintaining excellent resolution. number of clock cycles, n-bit adc the number of clock cycles dete rmines ?n? in the n-bit adc; 2 n clock cycles is a n-bit adc. n is programmable in the command register in the width function. depending on the application, a good balance of speed, and resolution has to be considered when deciding for n. for fast and quick measurement, choose the smallest n = 4. for maximum resolution without regard of time, choose n = 16. table 12 compares the tradeoff between integration time and resolution. see equations 10 and 11 for the relation between integration time and n. see equation 3 for the relation of n and resolution. external scaling resistor r ext and f osc the isl29004 use an external resistor r ext to fix its internal oscillator frequency, f osc . consequently, r ext determines the fosc, integration time and the fsr of the device. fosc, a dual speed mode oscillator, is inversely proportional to r ext . for user simplicity, the proportionality constant is referenced to fixed constants 100k and 655khz: fosc1 is oscillator frequency when range1 or range2 are set. this is nominally 327khz when r ext is 100k . fosc2 is the oscillator frequency when range3 or range4 are set. this is nominally 655khz when r ext is 100k . when the range/gain bits are set to range1 or range2, fosc runs at half speed comapred to when range/gain bits are set to range3 and range4. the automatic fosc adjustment feature allows significant improvement of signal-to-noise ratio when detecting very low lux signals. integration time or conversion time integration time is the per iod during which the device?s analog-to-digital adc converter samples the photodiode current signal for a lux measurement. integration time, in other words, is the time to co mplete the conversion of analog photodiode current into a digital signal-number of counts. integration time affects the measurement resolution. for better resolution, use a longer integration time. for short and fast conversions use a shorter integration time. the isl29004 offer user flexibility in the integration time to balance resolution, speed and nois e rejection. integration time can be set internally or externally and can be programmed in the command register 00(hex) bit 5. integration time in internal timing mode this timing mode is programmed in the command register 00(hex) bit 5. most applications will be using this timing mode. when using the internal timing mode, f osc and n-bits resolution determine the integration time. t int is a function of the number of clock cycles and fosc. n = 4, 8, 12, and16. n is the nu mber of bits of resolution. 2 n therefore is the number of clock cycles. n can be programmed at the command re gister 00(hex) bits 1 and 0. table 12. resolution and integration time selection n range1 fosc = 327khz range4 fosc = 655khz tint (ms) resolution lux/count tint (ms) resolution (lux/count) 16 200 0.01 100 1 12 12.8 0.24 6.4 16 8 0.8 3.90 0.4 250 4 0.05 62.5 0.025 4000 r ext = 100k (eq. 6) f osc1 1 2 -- - 100k r ext ------------------ 655 khz = (eq. 7) fosc2 100k r ext ------------------ 655 khz = (eq. 8) f osc 1 1 2 -- - f osc 2 () = t int 2 n 1 f osc ------------- = (eq. 9) for internal timing mode only isl29004
10 fn6221.0 december 21, 2006 since fosc is dual speed depending on the gain/range bit, t int is dual time. the integration time as a function of r ext and n is: t int1 is the integration time when the the device is configured for internal timing mode and gain/range is set to range1 or range2. t int2 is the integration time when the the device is configured for internal timing mode and gain/range is set to range3 or range4. integration time in external timing mode this timing mode is programmed in the command register 00(hex) bit 5. external timing mode is recommended when integration time can be synchronized to an external signal such as a pwm to eliminate noise. for mode0 or mode1 operation, the integration starts when the sync_iic command is sent over the i 2 c lines. the device needs two sync_iic commands to complete a photodiode conversion. the integration then stops when another sync_iic command is received. writing a logic 1 to the sync_iic bit ends the current adc integration and starts another one. for mode3, the operation is a sequential mode0 and mode1. the device needs three sync_iic commands to complete two photodiode measurments. the 1s t sync_iic command starts the conversion of the diode1. the 2nd sync_iic completes the conversion of diode1 and starts the conversion of diode2. the 3rd sync_iic pules ends the conversion of diode2 and starts over again to commence conversion of diode1. the integration time, t int , is determined by the following equation: i i2c is the number of i 2 c clock cycles to obtain the t int. f i2c is the i 2 c operating frequency the internal oscillator, f osc , operates identically in both the internal and external timing modes, with the same dependence on r ext . however, in external timing mode, the number of clock cycles per integration is no longer fixed at 2 n . the number of clock cycles varies with the chosen integration time, and is limited to 2 16 = 65,536. in order to avoid erroneous lux readings the integration time must be short enough not to allow an over flow in the counter register. f osc = 327khz*100k /r ext . when range/gain is set to range1 or range2. f osc = 655khz*100k /r ext . when range/gain is set to range3 or range4. noise rejection in general, integrating type adc?s have an excellent noise- rejection characteristics for periodic noise sources whose frequency is an integer multiple of the integration time. for instance, a 60hz ac unwanted signal?s sum from 0ms to k*16.66ms (k = 1,2...k i ) is zero. similarly, setting the device?s integration time to be an integer multiple of the periodic noise signal, greatly improves the light sensor output signal in the presence of noise. design example 1 the isl29004 will be designed in a portable system. the ambient light conditions that th e device will be exposed to is at most 500lux which is a good office lighting. the light source has a 50/60hz power line noise which is not visible by the human eye. the i2c clock is 10khz. solution 1 - using internal timing mode in order to achieve both 60hz and 50hz ac noise rejection, the integration time needs to be adjusted to coincide with an integer multiple of the ac noise cycle times. t int = i(1/60hz) = j(1/50hz). the first instance of integer values at which t int rejects both 60hz and 50hz is when i = 6, and j= 5. t int = 6(1/60hz) = 5(1/50hz) t int = 100ms next, the gain/range needs to be determined. based on the application condition given, lux(max) = 500lux, a range of 1000lux is desirable. this corresponds to a gain/range range1 mode. also impose a resolution of n = 16-bit. hence we choose equation 10 to determine r ext . table 13. integration times for typical r ext values r ext (k ) range1 range2 range3 range4 n = 16-bit n = 12-bit n = 12-bit n = 4 50 100 6.4 13 0.013 100** 200 13 26 0.025 200 400 26 52 0.050 500 1000 64 128 0.125 *integration time in milliseconds **recommended r ext resistor value t int 12 n r ext 327khz 100k ---------------------------------------------- = (eq. 10) t int 22 n r ext 655khz 100k ---------------------------------------------- = (eq. 11) t int i i2c f i2c ---------- = (eq. 12) t int 65,535 f osc ----------------- - < (eq. 13) r ext t int 327khz 100 k 2 n ----------------------------------------------------------------- = r ext 50k = for internal timing mode and gain/range is set to range3 or range (eq. 14) isl29004
11 fn6221.0 december 21, 2006 the full scale range, fsr, needs to be determined. from equation 3: the effective transfer function becomes: solution 2 - using external timing mode from solution 1, the desired integration time is 100ms. note that the r ext resistor only determines the inter oscillator frequency when using external timing mode. instead the integration time is the time between two sync_iic commands sent through the i 2 c. the programmer determines how many i 2 c clock cycles to wait betw een two external timing commands. i i2c = f i2c * t int = number of i 2 c clock cycles i i2c = 10khz * 100ms i i2c = 1,000 i 2 c clock cycles. an exte rnal sync_iic command sent 1,000 cycles af ter another sync_iic command rejects both 60hz and 50hz ac noise signals. next is to pick an arbitrary r ext = 100k and to choose the gain/range mode. for a maximum 500lux, range1 is adequate. from equation 3: the effective transfer function becomes: data is the sensor reading data located in data registers 04(hex) and 05(hex) counter is the timer counter value data located in data registers 06(hex) and 07(hex) . in this sample problem, counter = 1000. light source detection and infra-red rejection any filament type light source has a high presence of infrared component invisible to the human eye. a white fluorescent lamp, on the other hand has a low ir content. as a result, output sensitivity may vary depending on the light source. maximum attenuation of ir can be achieved by properly scaling the readings of diode1 and diode2. the user obtains data reading from sensor diode 1, d1, which is sensitive to visible and ir, then reading from sensor diode 2, d2 which is mostly sensitive from ir. t he graph on figure 7 shows the effective spectral response after applying equation 15 of the isl29003 from 400nm to 1000nm. the equation below describes the method of cancelling ir in internal timing mode. where: d3 = lux amount in number of counts less ir presence d1 = data reading of diode 1 d2 = data reading of diode 2 n = 1.355. this is a fudge factor to scale back the sensitivity up to ensure equation 4 is valid. k = 3.355. this is a scaling factor for the ir sensitive diode 2. flat window lens design a window lens will surely limit the viewing angle of the isl29004. the window lens should be placed directly on top of the device. the thickness of the lens should be kept at minimum to minimize loss of power due to reflection and also to minimize loss of loss due to absorption of energy in the plastic material. a thickness of t = 1mm is recommended for a window lens design. the bigger the diameter of the window lens the wider the viewing angle is of the isl29001. table 16 shows the recommended dimensions of the optical window to ensure both +35 and +45 viewing angle. these table 14. solution1 summary to example design problem design parameter value t int 100ms r ext 50k gain/range mode range1 = 1000lux fsr 2000lux # of clock cycles 2 16 transfer function fsr 1000lux 100k 50k ------------------ = fsr 2000 l ux = e data 2 16 ------------- 2000 l ux = e data 2 16 ---------------- - 2000lux = fsr 1000lux 100k 100k ------------------ = fsr 1000 l ux = e data counter ------------------------------- - 1000 l ux = table 15. solution2 summary to example design problem design parameter value t int 100ms r ext 100k gain/range mode range1 = 1000lux fsr 1000lux # of clock cycles counter = 1000 transfer function e data counter ------------------------------- - 1000lux = d3 n d1 kd2 ? () = (eq. 15) isl29004
12 fn6221.0 december 21, 2006 dimensions are based on a window lens thickness of 1.0mm and a refractive index of 1.59. window with light guide design if a smaller window is desired while maintaining a wide effective viewing angle of the is l29004, a cylindrical piece of transparent plastic is needed to trap the light and then focus and guide the light on to the device. hence the name light guide or also known as light pipe. the pipe should be placed directly on top of the device with a distance of d1 = 0.5mm to achieve peak performance. the light pipe should have minimum of 1.5mm in diameter to ensure that whole area of the sensor will be exposed. see figure 5. d lens ? t d1 d total ? = viewing angle window lens isl29003/4 figure 4. flat window lens table 16. recommended dimensions for a flat window design d total d1 d lens @ 35 viewing angle d lens @ 45 viewing angle 1.5 0.50 2.25 3.75 2.0 1.00 3.00 4.75 2.5 1.50 3.75 5.75 3.0 2.00 4.30 6.75 3.5 2.50 5.00 7.75 t = 1 thickness of lens d1 distance between isl29001 and inner edge of lens d lens diameter of lens d total distance constraint between the isl29001 and lens outer edge * all dimensions are in mm. d lens t l d lens light pipe isl29003/isl29004 d 2 d 2 > 1.5mm figure 5. window with light guide/pipe isl29004
13 fn6221.0 december 21, 2006 suggested pcb footprint footprint pads should be a nominal 1-to-1 correspondence with package pads. the large exposed central die-mounting paddle in the center of the package has no electrical connection. it is, however, recommended to have the thermal pad soldered to gnd for package reliability. layout considerations the isl29004 is relatively insensitive to layout. like other i 2 c devices, it is intended to provide excellent performance even in significantly noisy environments. there are only a few considerations that will ensure best performance. route the supply and i 2 c traces as far as possible from all sources of noise. use two power-supply decoupling capacitors, 4.7f and 0.1f, placed close to the device. typical circuit a typical application for the isl29004 is shown in figure 7. additional i 2 c address select pins a0 and a1 are available for the isl29004 so a maximum of four isl29004 devices can be tied on the same i 2 c bus line. soldering considerations convection heating is recommended for reflow soldering; direct-infrared heating is not recommended. the isl29004?s plastic odfn package does not require a custom reflow soldering profile, and is qualified up to +260c. a standard reflow soldering profile with a +260c maximum is recommended. special handling odfn8 is rated as jedec moisture level 4. standard jedec level 4 procedure should be followed: 72hr floor life at less than +30c 60% rh. when baking the device, the temperature required is +110c or less due to its special molding compound. figure 6. suggested pcb footprint dimensions in mm figure 7. isl29004 typical circuit vdd 1 gnd 2 rext 3 a0 4 a1 5 int 6 scl 7 sda 8 isl29004 vdd 1 gnd 2 rext 3 a0 4 a1 5 int 6 scl 7 sda 8 isl29004 rext1 100k rext2 100k c1 0.1uf i2c slave_44 c2 0.1uf vdd vdd i2c slave_45 microcontroller sda scl i2c master vdd 1 gnd 2 rext 3 a0 4 a1 5 int 6 scl 7 sda 8 isl29004 rext3 res1 c3 0.1uf vdd i2c slave_46 vdd 1 gnd 2 rext 3 a0 4 a1 5 int 6 scl 7 sda 8 isl29004 rext4 res1 c4 0.1uf vdd i2c slave_47 r1 10k r2 10k isl29004
14 fn6221.0 december 21, 2006 typical performance curves (r ext = 100k ) figure 8. spectral response figure 9. d1 and d2 fluorescent light source response figure 10. d1 and d2 halogen light source respo nse figure 11. d1 and d2 sunlight response figure 12. d1 and d2 incandescent light source response figure 13. radiation pattern 0 10 20 30 40 50 60 70 80 90 100 300 400 500 600 700 800 900 1000 1100 wavelength (nm) normalized response (%) d3 = n(d1 - kd2) n = 1.3, k = 3.355 d2 normalized d3 effective response d1 normalized - 10k 20k 30k 40k 50k 60k 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k luminance (lux) number of counts 6 7 8 9 10 11 12 13 14 d1/d2 ratio d1 fluorescent light source range3 d2 0 10k 20k 30k 40k 50k 60k 01k2k3k4k5k6k7k8k9k10k luminance (lux) number of counts 2 3 6 7 8 9 10 11 12 13 14 d1/d2 ratio halogen light source range3 d2 4 5 d1 0 10k 20k 30k 40k 50k 60k 01k2k3k4k5k6k7k8k9k10k luminance (lux) number of counts 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d1/d2 ratio sunlight source range3 d2 d1 - 10k 20k 30k 40k 50k 60k - 1k2k3k4k5k6k7k8k9k10k luminance (lux) number of counts 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d1/d2 ratio incandescent bulb range3 d1 d2 radiation pattern luminosity angle relative sensitivity isl29004
15 fn6221.0 december 21, 2006 figure 14. supply current vs supply voltage figure 15. output code for 0 lux vs supply voltage figure 16. output code vs supply voltage figure 17. oscillator frequency vs supply voltage figure 18. supply current vs temperature figure 19. output code for 0 lux vs temperature typical performance curves (r ext = 100k ) (continued) 2.0 2.3 2.6 2.9 3.2 3.5 3.8 320 306 292 278 264 250 supply current (a) supply voltage (v) t a = +27c command = 00h 5000 lux 200 lux 2.0 2.3 2.6 2.9 3.2 3.5 3.8 10 8 6 4 2 0 output code (counts) supply voltage (v) t a = +27c command = 00h 0 lux range 2 2.0 2.3 2.6 2.9 3.2 3.5 3.8 1.015 1.010 1.005 1.000 0.995 0.990 output code ratio (% from 3v) supply voltage (v) 5000 lux 200 lux t a = +27c command = 00h 0 lux 2.0 2.3 2.6 2.9 3.2 3.5 3.8 320.0 319.5 319.0 318.5 318.0 oscillator frequency (khz) supply voltage (v) -60 -20 20 60 100 315 305 295 285 275 265 supply current (a) temperature (c) v dd = 3v command = 00h 5000 lux 200 lux -60 -20 20 60 100 10 8 6 4 2 0 output code (counts) temperature (c) v dd = 3v command = 00h 0 lux isl29004
16 fn6221.0 december 21, 2006 figure 20. output code vs temperature figure 21. oscillator frequency vs temperature typical performance curves (r ext = 100k ) (continued) -60 -20 20 60 100 1.080 1.048 1.016 0.984 0.952 0.920 output code ratio (% from +25c) temperature (c) v dd = 3v command = 00h 5000 lux range 3 200 lux range 1 -60 -20 20 60 100 330 329 328 327 326 325 oscillator frequency (khz) temperature (c) v dd = 3v isl29004
17 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6221.0 december 21, 2006 isl29004 optical dual flat no-lead family (odfn) top view 12 3 54 4 2x 0.10 c 2x 0.10 c a b typ. 1 2 3 46 (e2) (d2) pin bottom view 3 2 6 1 8 4 5 7 6 ld odfn 8 ld odfn detail x plane seating (all leads 0.08 c and exposed pad) 0.10 c side view see (c) a a1 d a 0.10 c e b 5 #1 i.d. 3 3 l b bottom view (2.0x2.1 body) 0.10 c a b b (3.0x3.0 body) (d2) 3 pin #1 i.d. typ. l e1 e (e2) 3 detail "x" e c c 2 e1 0.10 c a b typ. 1 2 3 45 (e2) (d2) pin 5 ld odfn #1 i.d. 3 3 l b bottom view (2.0x2.1 body) e e1 5 mdp0052 optical dual flat no-lead family symbol odfn5 odfn6 odfn8 tolerance note a 0.70 0.70 0.70 0.05 a1 0.02 0.02 0.02 +0.03/-0.02 b 0.30 0.30 0.30 0.05 c 0.20 0.20 0.20 reference 2 d 2.00 2.00 3.00 basic d2 1.35 1.35 2.29 reference 3 e 2.10 2.10 3.00 basic e2 0.65 0.65 1.40 reference 3 e 0.65 0.65 0.65 basic e1 1.30 1.30 1.95 basic l 0.35 0.35 0.40 0.05 rev. 4 5/06 notes: 1. dimensioning and tolerancing per asme y14.5m - 1994. 2. exposed lead at side of package is a non-functional feature. 3. dimension d2 and e2 define the size of the exposed pad. 4. odfn 5 ld version has no cent er lead (shown as dashed line).

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